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TH58NVG5S0FTA20 toshiba mos digital integrated circuit silicon gate cmos 32 gbit (4 g 8 bit ) cmos nand e 2 prom description the th58nvg5s0f is a single 3.3v 32 gbit ( 36 , 305 , 895 , 424 bits) nand electrically erasable and programmable read - only memory (nand e 2 prom) organized as (4096 + 232 ) bytes 64 pages 16384 blocks. the device has two 4328 - byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4328 - byte increments. the erase operation is impleme nted in a single block unit (256 kbytes + 14.5 kbytes: 4328 bytes 64 pages). the th58nvg5s0f is a serial - type memory device which utilizes the i/o pins for both address and data input/output as well as for command inputs. the erase and program operations are automatical ly executed making the device most suitable for applications such as solid - state file storage, voice recording, image file memory for still cameras and other systems which require high - density non- volatile memory data storage. features ? organization x8 me mory cell array 4328 2 56 k 8 4 register 4328 8 page size 4328 bytes block size (256 k + 14.5 k) bytes ? modes read , reset , auto page program, auto block erase, status read, page copy, multi page program, multi block erase, multi page copy, multi page read ? mode control serial input / output command control ? number of valid blocks min 16064 blocks max 16384 blocks ? power supply v cc = 2. 7 v to 3.6 v ? acce ss time cell array to register 30 s max serial read cycle 25 ns min (cl= 10 0 pf) ? progra m/erase time auto page program 30 0 s /page typ. auto block erase 3 ms/block typ. ? operating current read (25 ns cycle) 30 ma max . program (avg.) 30 ma max erase (avg.) 30 ma max standby 20 0 a max ? package tsop i 48 -p- 1220- 0.50 c ? 4 bit ecc for each 512 byte is required. 201 1- 07 -01c 1
TH58NVG5S0FTA20 nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc psl nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 nc nc nc nc nc by / ry 2 by / ry 1 re ce 1 ce 2 nc v cc v ss nc nc cle ale we wp nc nc nc nc nc pin a ssignment (top view) pinnames i/o1 to i/o8 i/o port ce 1 chip enable (chip a,b) ce 2 chip enable (chip c,d) we write enable re read en able cle command latch enable ale address latch enable psl power on select wp write protect by / ry 1 ready/busy (chip a,b) by / ry 2 ready/busy (chip c,d) v cc power supply v ss ground 8 8 t h 58 n vg 5s0f t a2 0 201 1- 07 -01c 2
TH58NVG5S0FTA20 block di agram i/o1 i/o8 psl ce 1 cle ale we re by / ry 1 to wp i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by / ry v cc v ss row address buffer decoder address register ce 2 by / ry 2 i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by / ry v cc v ss row address buffer decoder (chip a, b) (chip c, d) addr ess r e gi ster 201 1- 07 -01c 3
TH58NVG5S0FTA20 absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 to v cc + 0.3 ( 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55 to 150 c t opr operating temperature 0 to 70 c capacitance * (ta = 25 c, f = 1 mhz ) symb0l parameter condition min max unit c in input v in = 0 v ? 40 pf c out output v out = 0 v ? 40 pf * this parameter is periodically sampled and is not tested for every device. 201 1- 07 -01c 4
TH58NVG5S0FTA20 valid blocks symbol parameter min t y p. max unit n vb number of valid blocks 16064 ? 16384 blocks note: the device occasionally contains unusable blocks. refer to application note (13) toward the end of this document. t he first block (block 0) is guaranteed to be a valid block at the time of shipment. the specification for the minimum number of valid blocks is applicable over lifetime the number of valid blocks is on the basis of single plane operations, an d this may be decreased with two plane operations. recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 ? 3.6 v v ih high level input voltage 2.7 v v cc 3.6 v vcc x 0.8 ? v cc + 0. 3 v v il low level input voltage 2.7 v v cc 3.6 v ? 0. 3 * ? v cc x 0.2 v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta = 0 to 70 , v cc = 2.7 to 3.6v ) symbol parameter condition min typ. max unit i il input leakage current v in = 0 v to v cc ? ? 10 a i lo output leakage current v out = 0 v to v cc ? ? 10 a i cco0 * 1 power on reset current psl = gnd or nu ? ? 30 ma psl = v cc , ffh command input after power on ? ? 30 i cco1 *2 serial read current ce = v il , i out = 0 ma, t cycle = 25 ns ? ? 30 ma i cco2 *2 programming current ? ? ? 30 ma i cco3 *2 erasing current ? ? ? 30 ma i ccs standby current ce = v cc ? 0.2 v , wp = 0 v/v cc , psl = 0 v/v cc /nu ? ? 20 0 a v oh high level output voltage i oh = ? 0. 4 ma 2.4 ? ? v v ol low level output voltage i ol = 2 .1 ma ? ? 0. 4 v i ol ( by / ry ) output current of by / ry pin v ol = 0.4 v ? 8 ? ma *1 refer to application note (2) for detail *2 icco1/2/3 are the value of one chip, and an unselected chip is in standby mode. 201 1- 07 -01c 5
TH58NVG5S0FTA20 ac characteristics and recommended operating conditions (ta = 0 to 70 , v cc = 2.7 t o 3.6v ) symbol parameter min max unit t cls cle setup time 12 ? ns t clh cle hold time 5 ? ns t cs ce setup time 20 ? ns t ch ce hold time 5 ? ns t wp write pulse width 12 ? ns t als ale setup time 12 ? ns t alh ale hold time 5 ? ns t ds data setup time 12 ? ns t dh data hold time 5 ? ns t wc write cycle time 25 ? ns t wh we high hold time 10 ? ns t ww wp high to we low 100 ? ns t rr ready to re falling edge 20 ? ns t rw ready to we falling edge 20 ? ns t rp read pulse width 12 ? ns t rc read cycle time 25 ? ns t rea re access time ? 20 ns t cea ce access time ? 25 ns t clr cle low to re low 10 ? ns t ar ale low to re low 10 ? ns t rho h re h igh to output hold time 25 ? ns t rloh re low to output hold time 5 ? ns t rhz re high to output high impedance ? 60 ns t chz ce high to output high impedance ? 20 ns t csd ce high to ale or cle don t care 0 ? ns t reh re high hold time 10 ? ns t ir output - high - impedance - to - re falling edge 0 ? ns t rhw re high to we low 60 ? ns t whc we high to ce low 30 ? ns t whr we high to re low 60 ? ns t r memory cell array to starting address ? 30 s t dcbsyr1 data cache busy in read cache (following 31h and 3fh) ? 30 s t dcbsyr2 data cache busy in page copy (following 3ah) ? 35 s t wb we high t o busy ? 100 ns t rst device reset time (ready/read/program/erase) ? 10/10/30/500 s *1: tcls and tals can not be shorter than twp *2: tcs should be longer than twp + 8ns. 201 1- 07 -01c 6
TH58NVG5S0FTA20 ac test conditions parameter condition v cc : 2. 7 to 3.6v input level 0v to vcc input pulse rise and fall time 3 ns input comparison level vcc / 2 output data comparison level vcc / 2 output load c l ( 10 0 pf ) + 1 ttl note: busy to ready time depends on the pull - up resistor tied to the by / ry pin. (refer to applic ation note (9) toward the end of this document.) programming and erasing characteristics (ta = 0 to 70 , v cc = 2.7 to 3.6v ) symbol parameter min typ. max unit notes t prog average programming time ? 300 700 s t dcbsyw1 data cache busy time in write cache ( following 11h) ? 0.5 1 s t dcbsyw2 data cache busy time in write cache ( following 15h) ? ? 7 00 s (2) n number of partial program cycles in the same page ? ? 4 (1) t berase block erasing time ? 3 10 ms (1) refer to application note (12) toward the end of this document. (2) t dcbsyw2 depends on the timing between internal programming time and data in time. data output when treh is long, output buffers are disabled by /re=high, and the hold time of data output depend on trhoh ( 25ns min). on thi s condition, waveforms look like normal serial read mode. when treh is short, output buffers are not disabled by /re=high, and the hold time of data output depend on trloh ( 5ns min). on this condition, output buffers are disabled by the rising edge of cle ,ale,/ce or falling edge of /we, and waveforms look like extended data output mode. 201 1- 07 -01c 7
TH58NVG5S0FTA20 timing diagrams latch timing diagram for command/address/data command input cycle timing diagram cle ale ce re we hold time t dh setup time t ds i/o : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale i/o 201 1- 07 -01c 8
TH58NVG5S0FTA20 address input cycle timing diagram data input cycle timing diagram we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce i/o d in 4327* t dh t ds t dh t ds t cs t cls t ch t cs t alh pa16 to 18 pa8 to 15 ca8 to 12 : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp ca0 to 7 t dh t ds t cs t cs ce we ale i/o t dh t ds t wp t wh t dh t ds t wp t wh t wc t dh t ds t wp t wh t wc pa0 to 7 t clh t ch t ch 201 1- 07 -01c 9
TH58NVG5S0FTA20 serial read cycle timing diagram status read cycle timing diagram t reh t chz ce t rhz t rea t rc t rr t rhz t rea t rhz t rea re by / ry i/o t rh oh t rhoh t rhoh t rp t rp t rp : v ih or v il t cea t cea : v ih or v il * : 70h represents the hexadecimal number t whr we t dh t ds t cls t clr t cs t clh t ch t wp status output 70h* t whc t ir t rea t rhz t chz ce cle re by / ry i/o t rhoh t cea 201 1- 07 -01c 10
TH58NVG5S0FTA20 read cycle timing diagram read cycle timing diagram: when interrupted by ce 30h pa16 to 18 pa8 to 15 pa0 to 7 ca8 to 12 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clr t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea col. add. n data out from col. add. n t dh t ds 00h d out n d out n + 1 by / ry t cea 30h pa16 to 18 pa8 to 15 pa0 to 7 ca8 to 12 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clr t r t dh t ds t wb t cs t cls t clh t c h t als t rc t rr t rea col. add. n t dh t ds 00h d out n d out n + 1 by / ry t chz t rhz t rhoh col. add. n t csd t cea 201 1- 07 -01c 11
TH58NVG5S0FTA20 read cycle with data cache timing diagram (1/2) 30h pa16 to 18 pa8 to 15 pa0 to 7 ca8 to 12 ca0 to 7 i/o t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t als t rc t rr t rea column address n * t dh t ds 00h d out 0 d out 1 by / ry tcea page address m d out 31h t dh t ds t wb t dcbsyr1 31h t dh t ds t wb d out 0 t rr t rea t dcbsyr1 t clr t clr tcea page address m col. add. 0 col. add. 0 page address m + 1 t rw t cs t cls t clh t ch 1 continues to of next page 1 * the column address will be reset to 0 by the 31h command input. t cs t cls t clh t ch t cs t cls t clh t ch t cs t cls t clh t ch 201 1- 07 -01c 12
TH58NVG5S0FTA20 read cycle with data cache timing diagram (2/2) continues from of last page 1 i/o we cle ce ale re by / ry d out t clr t wb 31h t dh t ds t wb 31h t dh t ds t rc t rr t rea page address m + 1 page address m + x t clr t wb t rc t rr t rea tcea 3fh t dh t ds d out 0 d out 1 d out t rc t rr t rea tcea page address m + 2 t dcbsyr1 t dcbsyr1 t dcbsyr1 t clr col. add. 0 col. add. 0 col. add. 0 tcea d out 0 d out 1 d out d out 0 d out 1 d out 1 t cs t cls t clh t ch t cs t cls t clh t ch t cs t cls t clh t ch make sure to terminate t he operation with 3fh command. 201 1- 07 -01c 13
TH58NVG5S0FTA20 column addre ss change in read cycle timing diagram (1/2) t clr i/o t cs t cls t clh t ch t wc t als t alh t r cle ce ale re t dh t ds t dh t ds t alh t wb t cs t cls t clh t ch t als t rc t rea tcea t rr page address p page address p column address a 00h ca0 to 7 t dh t ds ca8 to 12 t dh t ds pa0 to 7 t dh t ds pa8 to 15 t dh t ds pa16 to 18 t dh t ds 30h d out a d out a + 1 d out a + n we 1 continues from of next page 1 by / ry 201 1- 07 -01c 14
TH58NVG5S0FTA20 column address change in read cycle timing diagram (2/2) i/o t cs t cls t clh t ch 05h ca0 to 7 ca8 to 12 t wc t als t alh cle ce ale re t dh t ds t dh t ds t dh t ds column address b e0h t dh t ds t alh t cs t cls t clh t ch t als t rea d out a + n t rhw page address p column address b t rc t clr tcea t ir d out b + n d out b + 1 d out b 1 continues from of last page 1 we by / ry t whr 201 1- 07 -01c 15
TH58NVG5S0FTA20 data output timing diagram command i/o t rc t dh t rp t rp we cle ce ale re t rloh t reh t rea t rhz t rea t cs t cls t clh t ch t rp t rr t rea t rloh t ds by / ry t chz t rhoh t rhoh t cea dout dout t alh 201 1- 07 -01c 16
TH58NVG5S0FTA20 auto - program operation timing diagram ca0 to 7 t cls t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t prog t wb t ds t alh t als * ) m: up to 4 327 (byte input data for 8 device). column address n ca8 to 12 d in n d in m 10h 70h status output pa0 to 7 pa8 to 15 pa16 to 18 80h d in n+1 201 1- 07 -01c 17
TH58NVG5S0FTA20 auto - program operation with data cache timing diagram (1/3 ) t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw2 d in n d in n+1 t wb 80h t ds 15h t alh t als d in 4327 1 continues to 1 of ne xt page pa16 to 18 ca0 to ca12 is 0 in this diagram. ca0 to 7 ca0 to 7 ca8 to 12 pa0 to 7 pa8 to 15 201 1- 07 -01c 18
TH58NVG5S0FTA20 auto - program operation with data cache timing diagram (2/3) t cls t als t ds t dh ca0 to 7 80h we cle ce ale re by / ry t clh t ch t cs t cls t ds t dh t alh i/o : v ih or v il : do not input data while data is being output. pa0 to 7 ca8 to 12 t cs 1 continued from 1 of last page t dh t ds t dh t dcbsyw2 d in n d in n+1 t wb 80h t ds 15h t alh t als d in 4327 pa16 to 18 2 pa8 to 15 ca0 to 7 repeat a max of 62 times (in order to program pages 1 to 62 of a block). 201 1- 07 -01c 19
TH58NVG5S0FTA20 auto - program operation with data cache timing diagram (3/3) (note) make sure to terminate the operation with 80h - 10h - command sequence. if the oper ation is terminated by 80h - 15h command sequence, monitor i/o 6 (ready / busy) by issuing status read command (70h) and make sure the previous page program operation is completed. if the page program operation is completed issue ffh reset before next operat ion. 70h t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs 2 t dh t ds t dh t prog ( * 1) t wb t ds t alh t als d in 4327 continued from 2 of last page ( * 1) t prog : since the last page programming by 10h command is initiated after the previous cache program, the t prog during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page ? a a = (command input cycle + address input cycle + data input cycle time of the last page) if a exceeds the t prog of previous page, t prog of the last page is t prog max. 80h ca0 to 7 ca8 to 12 pa0 to 7 pa8 to 15 pa16 to 18 d in n d in n+1 10h s tatus 201 1- 07 -01c 20
TH58NVG5S0FTA20 multi - page program operation with data cache timing diagram (1/4) continues to 1 of next page t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw1 d in n d in n+1 t wb 81h t ds 11h t alh t als d in 4327 1 pa16 to 18 ca0 to 7 ca0 to 7 ca8 to 12 pa0 to 7 pa8 to 15 page address m district -0 201 1- 07 -01c 21
TH58NVG5S0FTA20 multi - page program operation with data cache timing diagram (2/4) : v ih or v il : do not input data while data is being output. t cls t als t ds t dh ca0 to 7 81h we cle ce ale re by / ry t clh t ch t cs t cls t ds t dh t alh i/o pa0 to 7 ca8 to 12 t cs 1 continued from 1 o f last page t dh t ds t dh t dcbsyw2 d in n d in n+1 t wb 80h t ds 15h t alh t als d in 4327 pa16 to 18 2 pa8 to 15 ca0 to 7 repeat a max of 63 times (in order to program pages 0 to 62 of a block). page address m district -1 201 1- 07 -01c 22
TH58NVG5S0FTA20 multi - page program operation with data cache timing diagram (3/4) i/o t cls t als t ds t dh 80h we cle ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw1 d in n d in n+1 t wb 81h t ds 11h t alh t als d in 4327 3 continues to 3 of next page pa16 to 18 ca0 to 7 ca0 to 7 ca8 to 12 pa0 to 7 pa8 to 15 page address m+n district - 0 2 201 1- 07 -01c 23
TH58NVG5S0FTA20 multi - page program operation with data cache timing diagram (4/4) (note) make sure to terminate the operation with 80h -10h - command sequence. if the operation is terminated by 8 1h- 15h command sequence, monitor i/o 6 (ready / busy) by issuing status read command (70h) and make sure the previous page program operation is completed. if the page program operation is completed issue ffh reset before next operation. ( * 1) t prog : since the last page programming by 10h command is initiated after the previous cache program, the t prog during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page ? a a = (command input cycle + address input cycle + data input cycle time of the last page) if a exceeds the t prog of previous page, t prog of the last page is t prog max. 71h t cls t als t ds t dh we cl e ce ale re by / ry : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs 3 t dh t ds t dh t prog ( * 1) t wb t ds t alh t als d i n 4327 continued from 3 of last page 81h ca0 to 7 ca8 to 12 pa0 to 7 pa8 to 15 pa16 to 18 d in n+1 10h status d in n page address m+n district - 1 201 1- 07 -01c 24
TH58NVG5S0FTA20 auto block erase timing diagram t cs 60h pa8 to 15 we cle ce ale re by / ry : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. auto block erase setup command i/o d0h 70h t wb t berase busy status read command erase start command status output t alh pa16 to 18 201 1- 07 -01c 25
TH58NVG5S0FTA20 multi block erase timing diagram 60h pa8 to 15 we cle ce ale re by / ry : v ih or v il t cs t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. d0h 71h t wb t berase busy status read command auto block erase setup command i/o1 to status output t alh repeat 2 times (district - 0,1) pa16 to 18 201 1- 07 -01c 26
TH58NVG5S0FTA20 copy back program with random data input we cle re i/ox ale ce t wc t wb r/b col add1 00h 35h 85h col add2 row add1 row add2 row add3 col add1 col add2 row add1 data1 datan 10h 70h i/o row add2 row add3 t r busy busy t wb t prog t whr copy back program dat a input command i/o1=0 successful program i/o1=1 error in program read status command column address row address column address row address 201 1- 07 -01c 27
TH58NVG5S0FTA20 id read operation timing diagram : v ih or v il we cle re t c ea ce ale i/o t a r id read command address 00 maker code device code t rea t cls t c s t d s t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 98h t rea d5h t rea t rea see table 5 see table 5 t rea see table 5 201 1- 07 -01c 28
TH58NVG5S0FTA20 pin functions the device is a serial access memory which utilizes time - sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command register from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading address information into the internal address register. address information is latched into the address register from the i/o port on the rising edge of we while ale is high. chip enable: (n) since the device contains two 8gbit chips, control for each chip by using ce 1 and ce 2. the chip not to be selected is disabled while ce is high. ce (n) signal is used to select the chip, and the chip goes into a low - power standby mode when ce goes high during the chip is in ready state. the ce signal is ignored when device is in busy state ( by/ry = l), such as during a program or erase or read operation, and wi ll not enter standby mode even if the ce input goes high . write enable: the we signal is used to control the acquisition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also incremented (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. write protect: the wp signal is used to protect the device from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usually used for protecting the data during the power -on/off sequence when input signals are invalid. ready/busy: (n) the by/ry output sig nal is used to indicate the operating condition of the device. the by/ry signal is in busy state ( by/ry = l) during the program, erase and read operations and will return to ready state ( by/ry = h) a fter completion of the operation. the output buffer for this signal is an open drain and has to be pulled - up to vccq with an appropriate resister. the device has by/ry 1 and by/ry 2 signal. by/ry 1 indi cates operating condition of the chip which has ce 1, and by/ry 2 indicates operating condition of the chip which has ce 2. power on select: psl the psl signal is used to select whether the device initialization should take place during the device power on or during the first reset. please refer to the application note (2) for details. we re wp ce by / ry 201 1- 07 -01c 29
TH58NVG5S0FTA20 schematic cell layout and address assignment the program operation works on page units while the erase operatio n works on block units . [8gbit ( chip a,b)] [8gbit ( chip c,d)] a page consists of 4328 bytes in which 4096 bytes are used for main memory storage and 232 bytes are for redundancy or for other uses. 1 page = 4328 bytes 1 block = 4328 bytes 64 pages = (256k + 14.5k) bytes capacity = 4328 bytes 64pages 16384 blocks table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 ca0 to ca12 : column address pa0 to pa1 8 : page address pa6 to pa1 8 : block address pa0 to pa5 : nand address in block first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l l ca12 ca11 ca10 ca9 ca8 third cycle pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 fourth cycle pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 fifth cycle l l l l l pa18 pa17 pa16 4328 524288 pages 8192 blocks 4096 4096 232 232 page buffer data cac he i/o8 i/o1 64 pages = 1 blo ck 8i/o 4328 524288 pages 8192 blocks 4096 4096 232 232 page buffer data cache i/o8 i/o1 64 pages = 1 block 8i/o 201 1- 07 -01c 30
TH58NVG5S0FTA20 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by command operations shown in table 3. address input, command input and data input/output are controlled by the cle, ale, ce , we , re , wp and psl signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 psl * 3 command input h l l h * 0v/ v cc /nu data input l l l h h 0v/ v cc /nu address input l h l h * 0v/ v cc /nu serial data output l l l h * 0v/ v cc /nu during program (busy) * * * * * h 0v/ v cc /nu during erase (busy) * * * * * h 0v/ v cc /nu dur ing read (busy) * * h * * * 0v/ v cc /nu * * l h ( * 2) h ( * 2) * 0v/ v cc /nu program, erase inhibit * * * * * l 0v/ v cc /nu standby * * h * * 0 v/v cc 0v/ v cc /nu h: v ih , l: v il , * : v ih or v il * 1: refer to application note ( 10 ) toward the end of this document regarding the wp signal when program or erase inhibit * 2: if ce is low during read busy, we and re must be held high to avoid unintended command/address input to the device or read to device . reset or status read command can be input during read busy. * 3: psl must be tied to either 0v or v cc or left unconnected(nu). 201 1- 07 -01c 31
TH58NVG5S0FTA20 table 3. command table (hex) first set second set acceptable while busy serial data input 80 ? read 00 30 co lumn address change in serial data output 05 e0 read with data cache 31 ? read start for last page in read cycle with data cache 3f ? auto page program 80 10 column address change in serial data input 85 ? auto program with data cache 80 15 multi page program 80 11 81 15 81 10 read for page copy (2) with data out 00 3a read for copy - back without data out 00 35 copy - back program without data out 85 10 auto program with data cache during page copy (2) 8c 15 auto program for last page during page copy (2) 8c 10 auto block erase 60 d0 page program with 2kb data 80 C 11 80 - 10 copy - back program with 2kb data 85 - 11 85 - 10 id read 90 ? status read 70 ? ? status read2 for chip a or c f1 ? ? status read2 for chip b or d f2 ? ? status read for multi - page program or multi block erase 71 ? ? reset ff ? ? table 4. read mode operation states cle ale ce we re i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active h: v ih , l: v il hex data bit assignment (example) 1 0 0 0 0 0 0 0 8 7 6 5 4 3 2 i/o1 serial data input: 80h 201 1- 07 -01c 32
TH58NVG5S0FTA20 device operation read mode read mode is set when the "00h" and 30h commands are issued to the command register. between the two commands, a start address for the read mode needs to be issued. after initial power on sequence, 00h command is latched into the internal command register. therefore read operation after power on sequence is excuted by the setting of only five address cycles and 30h command. refer to the fi gures below for the sequence and the block diagram (refer to the detailed timing chart.) . random column address change in read cycle by / ry we cle re 00h ce ale i/o busy 30h page address n column address m m m+1 m+2 page address n t r start - address input a data transfer operation from the cell array to the data cache via page buffer starts on the rising e dge of we in the 30h command input cycle (after the address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to ready state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. cell array select page n m m data cache page buffer i/o1 to 8: m = 4327 start - address input select page n m by / ry we cle 00h ce ale i/o col. m page n m busy page n 30h 05h e0h col. m m m + 1 m m + 1 m + 2 m + 3 m + 4 page n col. m start from col. m start from col. m during the serial data output from the data cache, the column address can be changed by inputting a new column address using the 05h and e0h commands. the data is read o ut in serial starting at the new column address. random column address change operation can be done multiple times within the same page. t r m + 2 m + 3 re 201 1- 07 -01c 33
TH58NVG5S0FTA20 read operation with read cache the device has a read operation with data cache that enables the high speed read opera tion shown below. when the block address changes, this sequence has to be started from the beginning. p age n + 2 if the 31h command is issued to the device, the data content of the next pag e is transferred to the page buffer during serial data out from the data cache, and therefore the tr (data transfer from memo ry cell to data register) will be reduced. 1 normal read. data is transferred from page n to data cache through page buffer. during this time period, the device outputs busy state for tr max. 2 after the ready/busy returns to ready, 31h command is is sued and data is transferred to data cache from page buffer again. this data transfer takes tdcbsyr1 max and the completion of this time peri od can be detected by ready/busy signal. 3 data of page n + 1 is transferred to page buffer from cell while the data of page n in data cache can be read out by /re clock simultaneously. 4 the 31h command makes data of page n + 1 transfer to data cache from pag e buffer after the completion of the transfer from cell to page buffer. the device outputs busy state for tdcbsyr1 max.. this busy period depends on the combination of the internal data transfer time from cell to page buffer and the serial data o ut time. 5 d ata of page n + 2 is transferred to page buffer from cell while the data of page n + 1 in data cache can be read out by /re clock simultaneously 6 the 3fh command makes the data of page n + 2 transfer to the data cache from the page buffer after the completion of the tran sfer from cell to page buffer. the device outputs busy state for tdcbsyr1 max.. this busy period depends on the combination of the internal data transfer time from cell to page buffer and the serial data out time. 7 data of page n + 2 in data cache can be read out, but since the 3fh command does not transfer the data from the memory cell to page buffer, the device can accept new command input immediately after the completion of serial data out. by / ry we cle 00h ce ale i/o t r 30h col. m page n 0 1 2 3 31h 31h 0 1 2 3 page address n column 0 4327 page address n + 1 4327 0 1 2 3 page address n + 2 4327 3fh data cache page buffer cell array 1 2 3 3 4 5 5 1 6 7 p age n p age n page n + 1 p age n 30 h 31 h & re clock p age n + 1 p age n + 2 p age n + 1 31 h & re clock page n + 2 3 fh & re clock 1 2 4 3 5 6 7 t dcbsyr1 t dcbsyr1 t dcbsyr1 re 201 1- 07 -01c 34
TH58NVG5S0FTA20 multi page read operation the device has a multi page read operation and multi page read with data cache operation.. (1) multi page read without data cache the sequence of command and address input is shown below. same page address ( pa0 to pa5 ) within each district has to be selected. the data transfer operation from the cell array to the data cache via page buffer starts on the rising edge of we in the 30h command input cycle (after the 2 districts address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to ready state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. selected page reading district 0 district 1 selected page by / ry 60 c ommand input page address pa0 to pa18 (district 0) tr address input 60 page address pa0 to pa18 (district 1) address input 30 a a by / ry 00 c ommand input column + page address ca0 to ca12, pa0 to pa18 (district 0) address input 05 column address ca0 to ca12 (district 0) address input e0 b b a a data output by / ry 00 c ommand input colu mn + page address ca0 to ca12, pa0 to pa18 (district 1) address input 05 column address ca0 to ca12 (district 1) address input e0 b b data output (district 0) (district 1) (3 cycle) (3 cycle) (5 cycle) (5 cycle) (2 cycle) 201 1- 07 -01c 35
TH58NVG5S0FTA20 (2) multi page read with data cache when the block address changes (increments) this sequenced has to be started from the beginning. the sequence of command and address input is shown below. same page address ( pa0 to pa5 ) within each district has to be selected. by / ry 60 c ommand input page address pa0 to pa18 (page m0 ; di strict 0) tr address input 60 page address pa0 to pa18 (page n0 ; district 1) address input 30 a a by / ry 00 c ommand input c olumn + page address ca0 to ca12, pa0 to pa18 (page m0 ; district 0) address input 05 column address ca0 to ca12 (district 0) address input e0 b a a data output by / ry 00 c ommand input column + page address ca0 to ca12, pa0 to pa18 (page n0 ; district 1) address input 05 column address ca0 to ca12 ( district 1) address input e0 b b data output (district 0) (district 1) 31 c c by / ry 00 c ommand input column + page address ca0 to ca12, pa0 to pa18 (pa ge m63 ; district 0) address input 05 column address ca0 to ca12 (district 0) address input e0 d c c data output by / ry 00 c ommand input column + page addre ss ca0 to ca12, pa0 to pa18 (page n63 ; district 1) address input 05 column address ca0 to ca12 (district 1) address input e0 d d data output (district 0) (district 1) 3f b return to a repeat a max of 63 times tdcbsyr1 tdcbsyr1 d 201 1- 07 -01c 36
TH58NVG5S0FTA20 (3) notes (a) internal addressing in relation with the districts to use multi page read operation, the internal addressing should be considered in relation with the district. ? the device contains four chips of nand eeprom. ? each internal chip consists from 2 districts. ? each district consists from 2048 erase blocks. ? the allocation rule is follows. (a) district 0: block 0, block 2, block 4, block 6, , block 4094 (b) district 1: block 1, block 3, block 5, block 7, , block 4095 (c) district 0: block 4096, block 4098, block 4100, block 4102, , block 8 190 (d) district 1: block 4097, block 4099, block 4101, block 4103, , block 8191 combination of (a) and (b) or (c) and (d) can only be selected. (b) address input restriction for the multi page read operation there are following restrictions in using m ulti page read; (restriction) district0 and district1 should be selected within the same chip. maximum one block should be selected from each district. same page address (pa0 to pa5) within two districts has to be selected. for example ; (60) [district 0, page address 0x00000] (60) [district 1, page address 0x00040] (30) (60) [district 0, page address 0x00001] (60) [district 1, page address 0x00041] (30) (acceptance) there is no order limitation of the district for the address input. for example, followi ng operation is accepted; (60) [district 0] (60) [district 1] (30) (60) [district 1] (60) [district 0] (30) it requires no mutual address relation between the selected blocks from each district. (c) wp signal make sure wp is held to high level when multi page read operation is performed 201 1- 07 -01c 37
TH58NVG5S0FTA20 auto page program operation the device carries out an automatic page program operation when it receives a "10h" program command after the address and data have been input. the sequence of command, address and data input is shown below. (refer to the detailed timing chart.) random column address change in auto page program operation the column address can be changed by the 85h command during the data input sequence of the a uto page program operation. two address input cycles after the 85h command are recognized as a new column address for the data input. after the new data is input to the new column address, the 10h command initiates the actual data program into the selected page automatically. the random column address change operation can be repeated multiple times within the same page. 80h page n col. m 85h din din 10h status din din din din col. m din din 70h busy data input selec ted page reading & verification program col. m col. m the data is transferred (programmed) from the data cache via the page buffer to the selected page on the rising edge of we fo llowing input of the 10h command. after programming, the programmed data is transferred back to the page buffer to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page program data input read& verification cle 80h ale i/o page p ce we col. m din 10h 70h din din din data status out re byry/ 201 1- 07 -01c 38
TH58NVG5S0FTA20 multi page program the device has a multi page program, which enables even higher speed program operation compared to auto page program. t he sequence of command, address and data input is shown bellow. (refer to the detailed timing chart.) although two planes are programmed simultaneously , pass/fail is not available for each page when the program operation completes. sta tus bit of i/o 1 is set to 1 when any of the pages fails. limitation in addressing with multi page program is shown below. multi page program note: any command between 11h and 81h is prohibited except 70h /f1h and ffh. data input 80h 11h plane 0 (2048 block) block 0 block 2 block 4092 block 4094 81h 10h plane 1 (2048 block) block 1 block 3 block 4093 block 4095 i/o0 ~ 7 r/ b i/o1 pass fail 1 0 tdcbsyw1 tprog ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : district0 pa7 ~ pa18 : valid 80h address & data input 11h ca 0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : district1 pa7 ~ pa1 8 : valid 81h address & data input 10h 70h note 201 1- 07 -01c 39
TH58NVG5S0FTA20 auto page program operation with data cache the device has an auto page program with data cache operation enabling the high speed program operation shown below. when the block address changes this sequenced has to be started from the beginning. by / ry cle ale i/o ce we page n 80h add add add add status output din 15h 70h din din page n + 1 80h add add add add 1 status output din 15h 70h din din page n + p 80h add add add add 3 4 status output din 10h 70h din din 5 6 data cache page buffer cell array p age n + p 1 2 3 4 5 5 6 p age n p age n + 1 data for p age n + p 3 add add add data for p age n data for p age n data for p age n + 1 data for p age n + 1 p age n + p ? 1 t dcbsyw2 t dcbsyw2 t prog (note) issuing the 15h command to the device after serial data input initiates the program operation w ith data cache 1 data for page n is input to data cache. 2 data is transferred to the page buffer by the 15h command. during the transfer the ready/busy outputs busy state (t dcbsyw2 ). 3 data is programmed to the selected page while the data for page n + 1 is input to the data cache. 4 by the 15h command, the data in the data cache is transferred to the page buffer after the programming of page n is completed. the device output busy state from the 15h command until the data cache becomes empty. the duration of this period depends on timing between the internal programming of page n and serial data input for page n + 1 (t dcbsyw2 ). 5 data for page n + p is input to the data cache while the data of the page n + p ? 1 is being programmed. 6 the programming with data cache is terminated by the 10h command. when the device becomes ready, it shows that the internal programming of the page n + p is completed. note: since the last page programming by the 10h command is initiated after the previous cache program, the tprog during cache programming is given by the following; t prog = t prog for the last page + t prog of the previous page ? ( command input cycle + address input cycle + data input cycle time of the previous page) re 2 201 1- 07 -01c 40
TH58NVG5S0FTA20 pass/fa il status for each page programmed by the auto page programming with data cache operation can be detected by the status read operation. ? i/o1 : pass/fail of the current page program operation . ? i/o2 : pass/fail of the previous page program operation . the pas s/fail status on i/o1 and i/o2 are valid under the following condition s. ? status on i/o1: page buffer read y /busy is ready state. the page buffer ready/busy is output on i/o6 by status r ead operation or by/ry pin after the 10h command ? sta tus on i/o2: data cache read/busy is ready state. the data cache ready/busy is output on i/o7 by status read operation or by/ry pin after the 15h command. 80 h 15h 70 h status out page 1 data cache busy page buffer busy page 1 page 2 70 h 70 h page 2 70 h 80 h 15h page n ? 1 80 h 10h page n page n ? 1 page n 70 h 80 h 15h i/o2 => i/o1 => invalid invalid page 1 invalid page n ? 2 invalid invalid invalid page n ? 1 page n page 1 page 2 70 h if the p age b uffer busy returns to ready before the next 80h command input, and if status read is done during this ready period, the status read provides pass/fail for page 2 on i/o1 and pass/fail resul t for page1 on i/o2 status out status out status out status out status out example) byry/ pin 201 1- 07 -01c 41
TH58NVG5S0FTA20 multi page program with data cache the device has a multi page program with data cache operation, which enables even higher speed program operation compared to auto page program with data cache as shown below. when the block address changes (increments) this sequenced has to be started from the beginning. the sequence of command, address and data input is shown below. (refer to the detailed timing chart.) after 15h or 10h pro gram command is input to device, physical programing starts as follows. for details of auto program with data cache, refer to auto page program with data cache . the data is transferred (programmed) from the page buffer to the selected page on the rising edge of /we following input of the 15h or 10h command. after programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does not succeed, the program/verify op eration is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page reading & verification program district 0 district 1 by / ry data input command for multi - page program data input 0 to 4327 15 81 80 11 10 81 80 11 data input command address input (district 0) data input 0 to 4327 dummy program command data input command data input 0 to 4327 address input (district 1) program with data cache com mand address input (district 0) dummy program command auto page program command data input 0 to 4327 address input (district1) data input command for multi - page program 201 1- 07 -01c 42
TH58NVG5S0FTA20 starting the above operation from 1st page of the selected erase blocks, and then r epea ting the operation total 64 times with incrementing the page address in the blocks, and then input the last page data of the blocks, 10h command executes final programming . make sure to terminate with 81 h- 10h - command sequence. in this full sequence, the command sequence is following. after the 15h or 10h command, the results of the above operation is shown through the 71h status read command. the 71h command status description is as below. status output i/o1 d escribes pass/fail condition of district 0 and 1(or data of i/o2 and i/o3). if one of the districts fails during multi page program operation, it shows fail . i/o2 to 5 shows the pass/fail condition of each district. for details on chip status1 and ch ip status2 , refer to section status read . i/o1 chip status1 : pass/fail pass: 0 fail: 1 i/o2 district 0 chip status1 : pass/fail pass: 0 fail: 1 i/o3 district 1 chip status1 : pass/fail pass: 0 fail: 1 i/o4 district 0 chip status2 : pass/fail pas s: 0 fail: 1 i/o5 district 1 chip status2 : pass/fail pass: 0 fail: 1 i/o6 ready/busy ready: 1 busy: 0 i/o7 data cache ready/busy ready: 1 busy: 0 i/o8 write protect protect: 0 not protect: 1 10 or15 71 pass i/o status read command fail by / ry 15 15 10 15 81 81 81 81 11 11 11 11 80 80 80 80 1st 63 th 64th 201 1- 07 -01c 43
TH58NVG5S0FTA20 internal addressing in relation with the districts to use multi page program operation, the internal addressing should be considered in relation with the district. ? the device contains four chips of nand eeprom. ? each internal chip consists from 2 districts. ? each district consists from 2048 erase blocks. ? th e allocation rule is follows. (a) district 0: block 0, block 2, block 4, block 6, , block 4094 (b) district 1: block 1, block 3, block 5, block 7, , block 4095 (c) district 0: block 4096, block 4098, block 4100, block 4102, , block 8190 (d) district 1: block 4097, block 4099, block 4101, block 4103, , block 8191 combination of (a) and (b) or (c) and (d) can only be selected. address input restriction for the multi page program with data cache operation there are following restrictions in using multi page program with data cache; (restriction) district0 and district1 should be selected within the same chip. maximum one block should be selected from each district. same page address (pa0 to pa5) within two districts has to be selected. for example ; ( 80) [district 0, page address 0x00000] (11) (81) [district 1, page address 0x00040] (15 or 10) (80) [district 0, page address 0x00001] (11) (81) [district 1, page address 0x00041] (15 or 10) (acceptance) there is no order limitation of the district for the address input. for example, following operation is accepted; (80) [district 0] (11) (81) [district 1] (15 or 10) (80) [district 1] (11) (81) [district 0] (15 or 10) it requires no mutual address relation between the selected blocks from each distric t. operating restriction during the multi page program with data cache operation (restriction) the operation has to be terminated with 10h command. once the operation is started, no commands other than the commands shown in the timing diagram is allowed to be input except for status read command and reset command. 201 1- 07 -01c 44
TH58NVG5S0FTA20 page copy (2) by using page copy (2), data in a page can be copied to another page after the data has been read out. when the block address changes (increments) this sequenced has to be started from the beginning. page copy (2) operation is as following. 1 data for page n is transferred to the data cache. 2 data for page n is read out. 3 copy page address m is input and if the data needs to be changed , changed data is input. 4 data cache for page m is transferred to the page buffer. 5 after the ready state, data for page n + p1 is output from the data cache while the data of page m is being programmed. when changing data, changed data is input. 1 3 4 5 2 t r t dcbsyw2 t dcbsyr2 byry/ 00 c ommand input address ca0 to ca12, pa0 to pa18 (page n) addres s input 30 address input 8c a data input 15 00 address input 3a data output address ca0 to ca12, pa0 to pa18 (page m) address ca0 to ca12, pa0 to pa18 (page n+p1) a data output col = 0 start col = 0 start data cache page buffer cell array 1 2 3 4 5 p age n data for p age n data for p age n p age m p age n + p1 data for p age n + p1 data for p age m 201 1- 07 -01c 45
TH58NVG5S0FTA20 6 copy page addre ss (m + r1) is input and if the data needs to be changed , changed data is input. 7 after programming of page m is completed, data cache for page m + r1 is transferred to the page buffer. 8 by the 15h command, the data in the page buffer is programmed to page m + r1 . data for page n + p2 is transferred to the data cache. 9 the data in the page buffer is programmed to page m + rn ? 1 . data for page n + pn is transferred to the data cache. by / ry 8 9 6 7 t dcbsyw2 t d cbsyr2 t dcbsyr2 when changing data, changed data is input. c ommand input address ca0 to ca12, pa0 to pa18 (page m+r1) b 00 address input 3a data output address input 8c data input 15 00 address input 3a data output address ca0 to ca12 , pa0 to pa18 (page n+p2) address ca0 to ca12, pa0 to pa18 (page n+pn) a b a col = 0 start col = 0 start data cache page buffer cell array 6 7 8 p age m data for p age m + r1 data for p age m + r1 data for p age n + p2 data for p age n + pn p age m + r1 page n + p2 p age n + p1 p age m + rn ? 1 page n + pn p age m + rn ? 1 9 201 1- 07 -01c 46
TH58NVG5S0FTA20 10 copy page address (m + rn) is input and if the data needs to be changed , changed data is input. 11 by issuing the 10h command, the data in the page buffer is programmed to page m + rn . (*1) since the last page progr amming by the 10h command is initiated after the previous cache program, the t prog here will be expected as the following, t prog = t prog of the last page + tprog of the previous page ? ( command input cycle + address input cycle + data output/input cycle time of the last page) note) this operation needs to be executed within district - 0 or district -1. data input is required only if previous data output needs to be altered. if the data has to be changed, locate the desired address with the column and page address input after the 8ch command, and change only the data that needs be changed. if the data does not have to be changed, data input cycles are not required. make sure wp is held to high level when page copy (2) operation is perfor med. also make sure the page copy operation is terminated with 8ch - 10h command sequence data cache page buffer cell array p age m + rn ? 1 data for p age m + rn data for p age m + rn p age n + pn 10 11 by / ry 10 11 t prog ( *1 ) c ommand input address ca0 to ca12, pa0 to pa18 (page m+rn) address input 8c data input 10 70 status output b b 201 1- 07 -01c 47
TH58NVG5S0FTA20 multi page copy (2) by using multi page copy (2), data in two pages can be copied to another pages after the data has been read out. when the each block address changes (increments) this sequenced has to be started from th e beginning. same page address (pa0 to pa5) within two districts has to be selected. t r byry/ 60 c ommand input address pa0 to pa18 (page m0 ; district 0) address input 30 a 00 address input e0 data output address ca0 to ca12, pa0 to pa18 (page m0) a 60 address input address pa0 to pa18 (page n0 ; district 1) 05 address input address ca0 to ca12 (col = 0) t dcbsyw1 00 address input 0 5 address input e0 b b data output address ca0 to ca12, pa0 to pa18 (page n0) address ca0 to ca12 (col = 0) 8c address input 11 data input address ca0 to ca12, pa0 to pa18 (page m0 ; district 0) byry/ a a 00 addre ss input 05 address input e0 data output address ca0 to ca12, pa0 to pa18 (page m1) address ca0 to ca12 (col = 0) byry/ 00 address input 05 address input e0 data output address ca0 to ca12, pa0 to pa18 (page n1) address ca0 to ca12 (col = 0) d d c c t dcbsyw2 8c address input 15 data input address ca0 to ca12, pa0 to pa18 (page n0 ; district 1) byry/ 60 address pa0 to pa18 (page m1 ; district 0) address input 3a 60 address input address pa0 to pa18 (page n1 ; district 1) c c b b t dcbsyr2 201 1- 07 -01c 48
TH58NVG5S0FTA20 t dcbsyw1 00 address input 05 address input e0 g g d ata output address ca0 to ca12, pa0 to pa18 (page n63) address ca0 to ca12 (col = 0) 8c address input 11 data input address ca0 to ca12, pa0 to pa18 (page m63 ; district 0) byry/ f f t dcbsyr2 byry/ 60 address pa0 to pa18 (page m63 ; distric t 0) address input 3a f 00 address input e0 data output address ca0 to ca12, pa0 to pa18 (page m63) f 60 address input address pa0 to pa18 (page n63 ; district 1) 05 address input address ca0 to ca12 (col = 0) e e t dcbsyw1 8c address input 11 data input address ca0 to ca12, pa0 to pa18 (page m1 ; district 0) byry/ e e d d 8c address input 15 data input address ca0 to ca12, pa0 to pa18 (page n1 ; district 1) t dcbsyw2 byry/ g g 8c address input 10 data input address ca0 to ca12, pa0 to pa18 (page n63 ; district 1) t prog (*1) note) this operation needs to be executed within each district. da ta input is required only if previous data output needs to be altered. if the data has to be changed, locate the desired address with the column and page address input after the 8ch command, and change only the data that needs be changed. if the data does not have to be changed, data input cycles are not required. make sure wp is held to high level when multi page copy (2) operation is performed. also make sure the multi page copy operation is terminated with 8ch - 10h command sequence ( * 1) t prog : since the last page programming by 10h command is initiated after the previous cache program, the t prog* during cache programming is given by the following equation. t prog = t prog of the last page + t prog of the previous page -a a = (command input cycle + address input cycle + data output/input cycle time of the last page) if a exceeds the t prog of previous page, t prog of the last page is t prog max. 201 1- 07 -01c 49
TH58NVG5S0FTA20 auto block erase the auto block erase operation starts on the rising edge of we after the erase start command d0h which follows the erase s etup command 60h . this two - cycle process for erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. the device automatically executes the erase and verify operations. multi block erase the multi blo ck erase operation starts by selecting two block addresses before d0h command as in below diagram. the device automatically executes the erase and verify operations and the result can be monitored by checking the status by 71h status read command. for details on 71h status read command, refer to section multi page program with data cache . internal addressing in relation with the districts to use multi block erase operation, the internal addressing should be considered in relation with the district. ? th e device contains four chips of nand eeprom. ? each internal chip consists from 2 districts. ? each district consists from 2048 erase blocks. ? the allocation rule is follows. (a) district 0: block 0, block 2, block 4, block 6, , block 4094 (b) district 1: blo ck 1, block 3, block 5, block 7, , block 4095 (c) district 0: block 4096, block 4098, block 4100, block 4102, , block 8190 (d) district 1: block 4097, block 4099, block 4101, block 4103, , block 8191 combination of (a) and (b) or (c) and (d) can onl y be selected. address input restriction for the multi block erase there are following restrictions in using multi block erase (restriction) district0 and district1 should be selected within the same chip. maximum one block should be selected from each d istrict. for example ; (60) [district 0] (60) [district 1] (d0) (acceptance) there is no order limitation of the district for the address input. for example, following operation is accepted; (60) [district 1] (60) [district 0] (d0) it requires no mutual a ddress relation between the selected blocks from each district. make sure to terminate the operation with d0h command. if the operation needs to be terminated before d0h command input, input the ffh reset command to terminate the operation . pass i/o fail by / ry 60 d0 70 block address input: 3 cycles status read command busy erase start command pass i/o fail by / ry 60 d0 71 block address input: 3 cycles district 0 status read command busy erase start command 60 block address input: 3 cycles district 1 201 1- 07 -01c 50
TH58NVG5S0FTA20 read for copy - back with data output timing guide copy - back operation is a sequence execution of read for copy - back and of copy- back program with the destination page address. a read operation with 35h command and the address of source page moves the whole 4328 byte dat a into the internal data buffer. bit errors are checked by sequential reading the data. in the case where there is no bit error, the data don t need to be reloaded. therefore copy - back program operation is initiated by issuing page - copy data - input command (85h) with destination page address. acutual programming operation begins after program confirm command (10h) is issued. once the program process starts, the read status register command (70h) may be enterd to read the status register. the system contoller can detect the completion of a program cycle by monitoring the by / ry output, or the status bit (i/o7) of the status register. when the copy - back program is complete, the write status bit (i/o1) may be checked. the command register remai ns in read status command mode until another valid command is written to the command register. during copy - back program, data modification i s possible using randam data input command (85h) as shown below. page copy - back program operation note: 1. copy - back program operation is allowed only within the same district . page copy - back program operation with random data input col. add.1,2 & page add.1,2,3 source address i/ox 00h r/ b add.(5cycles) i/o1 pass fail 1 0 col. add.1,2 & page add.1,2,3 destination address tr tprog 35h data output 85h add.(5cycles) 10h 70h col. add.1,2 & page add.1,2,3 source addres s i/ox 00h r/ b add.(5cycles) col. add.1,2 & page add.1,2,3 destination address tr tprog data output 35h 85h add.(5cycles) data 85h add.(2cycles) data 10h 70h col. add.1,2 there is no limitation for the number of repetitio n 201 1- 07 -01c 51
TH58NVG5S0FTA20 tw o - plane copy - back program operation multi page copy - back program is an extension of copy - back progr am, for a single plane with 4328 byte data registers. since the device is equipped with two memory planes, activating the two sets of 4328 byte data registers enable a simultaneous programming of two pages. same page address (pa0 to pa5) within two districts has to be selected. note: 1. copy - back program operation is allowed only within the same district . 2. any command between 11h and 81h is prohibited except 70h/f1h and ffh. i/ox 60h r/ b address(3cycle) 60h 35h tr address(3cycle) row add.1,2,3 pa0 ~ pa5 : valid pa6 : fixed low pa7 ~ pa18 : valid row add.1,2,3 pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : v alid 1 i/ox 00h r/ b address(5cycle) 05h e0h address(2cycle) col. add.1,2 & row add.1,2,3 ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed low pa7 ~ pa18 : valid col. add.1,2 ca0 ~ ca12 : valid 2 data output 1 i/ox 00h r/ b address(5cycle) 05h e0h address(2cycle) col. add.1,2 & row add.1,2,3 ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : valid col. add.1,2 ca0 ~ ca12 : valid d ata output 2 i/ox 85h r/ b add.(5cycles) 11h col. add.1,2 & row add.1,2,3 destination address ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed low pa7 ~ pa18 : valid 3 81h add.(5cycles) 10h 70h tdcbsyw1 tprog note *2 col. add.1,2 & row add.1,2,3 destin ation address ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : valid 3 plane0 source page target page (1) (3) (2) data field spare field plane1 source page target page (1) (3) (2) data field s pare field (1) : multi page read for copy back (2) : multi page random data out (3) : multi page copy - back program 201 1- 07 -01c 52
TH58NVG5S0FTA20 tw o - plane copy - back program operation with random data input note: 1. copy - back program operation is allowed only within the same district . 2. any command between 11h and 81h is prohibited except 70h/f1h and ffh. i/ox 60h r/ b address(3cycle) 60h 35h tr address(3cycle) page add.1,2,3 pa0 ~ pa 5 : valid pa6 : fixed low pa7 ~ pa18 : valid page add.1,2,3 pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : valid 1 i/ox 00h r/ b address(5cycle) 05h e0h address(2cycle) col. add.1,2 & page add.1,2,3 ca0 ~ ca1 2 : valid pa0 ~ pa5 : valid pa6 : fixed low pa7 ~ pa18 : valid col. add.1,2 ca0 ~ ca12 : valid 2 data output 1 i/ox 00h r/ b address(5cycle) 05h e0h address(2cycle) col. add.1,2 & page add.1,2,3 ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : valid col . add.1,2 ca0 ~ ca12 : valid data output 2 3 i/ox 85h r/ b add.(5cycles) data col. add.1,2 & page add.1,2,3 destination address ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed low pa7 ~ pa18 : valid 3 add.(2cycles) tdbsy col. a dd.1,2 85h data 11h 4 note *2 i/ox 81h r/ b add.(5cycles) data col. add.1,2 & page add.1,2,3 destination address ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : valid 4 add.(2cycles) tprog col. add.1,2 85h data 10h 201 1- 07 -01c 53
TH58NVG5S0FTA20 2kb program operation timing guide the device is designed also to support the program operation with 2kbyte data to offer the backward compatibility to the controller which uses the nand flash with 2kbyte page. the sequence of command, address and data input is shown below. (2kbx2) program operation note: 1. any command between 11h and 81h is prohibited except 70h /f1h and ffh (2kbx2) copy - back note: 1. copy - back is allowed only within the same memory district. 2. any command between 11h and 81h is prohibited except 70 h /f 1h and ffh. ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : valid pa7 ~ pa18 : valid i/o0 ~ 7 r/ b tdcbsyw1 tpro g 80h address & data input 11h 80h address & data input 10h 70h note col. add.1,2 & row add.1,2,3 2112 byte data ca0 ~ ca12 : valid pa0 ~ pa5 : must be same with the previous pa6 : must be same with the previous pa7 ~ pa1 8 : must be same with the previous col. add.1,2 & row add.1,2,3 2112 byte data tr i/ox r/ b col. add.1,2 & row add.1,2,3 source address 00h add.(5cycles) 35h data output 1 tdcbsyw1 i/ox r/ b 85h add.(5cycles) data 1 11h 85h add.(5cycles) data 10h tprog ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : valid pa7 ~ pa18 : valid col. add.1,2 & row add.1,2,3 destination address ca0 ~ ca12 : valid pa0 ~ pa5 : must be same with the previous pa6 : must be same with the previous pa7 ~ pa18 : must be same with the pr evious col. add.1,2 & row add.1,2,3 destination address 201 1- 07 -01c 54
TH58NVG5S0FTA20 (2kbx2) copy - back with random data input note: 1. copy - back is allowed only within the same memory district. 2. any command between 11h and 81h is prohibited except 70h /f 1h and ffh. tr i/ox r/ b col. add.1,2 & row add.1, 2,3 source address 00h add.(5cycles) 35h data output 1 i/ox 85h r/ b add.(5 cycles) data col. add.1,2 & row add.1,2,3 destination address ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : valid pa7 ~ pa18 : valid 1 add.(2cycles) tdcbsyw1 col. add.1,2 85h data 11h 2 note *2 i/ox 85h r/ b add.(5cycles) data col. add.1,2 & row add.1,2,3 destination address ca0 ~ ca12 : valid pa0 ~ pa5 : must be same with the previous pa6 : must be same with the previous pa7 ~ pa18 : must be same with the previous 2 add.(2cycles) tprog col. add.1,2 85h data 10h 201 1- 07 -01c 55
TH58NVG5S0FTA20 multi page copy - back using 4kb buffer ram the deveice consists of 4kb pages and can support multi plane program operation. the internal ram requirement for a controller is 8kb, but for those controllers which support less than 8kb ram, the sequence of command, address and data input is shown below for multi plane progra m operation. multi page co py - back with random data input note: 1. copy - back is allowed only within the same memory district. district0 target page (1) (6) (2) data field spare field district1 4kbyte 4kbyte source page source page target page (1) (6) data field spare field (1) : two - plane read for copy - back (2) : random data out on plane 0(up to 4328byte) (3) : random data in on plane 0(up to 43 28byte) (4) : random data out on plane 1(up to 4328byte) (5) : random data in on plane 1(up to 4328byte) (6) : two - plane program for copy - back (3) (4) (5) row add.1,2,3 tr i/ox r/ b add.(3cycle) add.(3cycle) 1 pa0 ~ pa5 : valid pa6 : fixed low pa7 ~ pa18 : valid row add.1,2,3 pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : valid ca0 ~ ca12 : fixed low pa0 ~ pa5 : fixed low pa6 : fixed low pa7 ~ pa18 : fixed low col. add.1,2 & row add.1,2,3 destination address tdcbsyw1 i/ox 85h r/ b add.(5cycle) col. add.1,2 up to 4328byte dout 2 col. add.1,2, ca0 ~ ca12 : valid col. add.1,2 & row add.1,2,3 ca0 ~ ca12 : fixed low pa0 ~ pa5 : fixed low pa6 : fixed high pa7 ~ pa18 : fixed low 1 add.(2cycle) din 85h din add.(2cycle) 05h e0h add.(5cycle) 00h 11h col. add.1,2 up to 4328byte dout ca0 ~ ca12 : valid col. add.1,2 & row add.1,2,3 add.(2cycle) 05h e0h add.(5cycle) 00h 60h 60h 35h ca0 ~ ca12 : va lid pa0 ~ pa5 : valid pa6 : fixed low pa7 ~ pa18 : valid col. add.1,2 & row add.1,2,3 destination address tprog i/ox 81h r/ b add.(5cycle) 70h col. add.1,2, 2 add.(2cycle) din 85h din 10h ca0 ~ ca12 : valid pa0 ~ pa5 : valid pa6 : fixed high pa7 ~ pa18 : valid 201 1- 07 -01c 56
TH58NVG5S0FTA20 id read the device contains id codes which can be used to identify the device type, t he manufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 0 1 0 1 0 1 d5h 3rd data chip number, cell type ? ? ? ? ? ? ? ? see table 4th data page size, block size ? ? ? ? ? ? ? ? see table 5th data plane number ? ? ? ? ? ? ? ? see table 3rd data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 90h 00h 98h d5 h see table 5 see table 5 we cle re t cea ce ale i/o t ar t rea id read command address 00 maker code device code see table 5 201 1- 07 -01c 57
TH58NVG5S0FTA20 4th data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 1 kb 2 kb 4 kb 8 kb 0 0 1 1 0 1 0 1 block size (without redundant area) 64 kb 126 kb 256 kb 512 k b 0 0 1 1 0 1 0 1 5th data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 plane number 1 plane 2 plane 4 plane 8 plane 0 0 1 1 0 1 0 1 201 1- 07 -01c 58
TH58NVG5S0FTA20 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/busy status of the device, determine the result (pass /fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port using re or ce after a 70h or f1h or f2h command input. this two signal control allows the syste m to poll the progress of each device in multiple memory connections even when ready/busy pins are common - wired. the status read can also be used during a read operation to find out the ready/busy status. the resulting information is outlined in table 6 and tabel 7. table 6. status output table definition page program block erase cache program read cache read i/o1 chip status1 pass: 0 fail: 1 pass/fail pass/fail invalid i/o2 chip status 2 pass: 0 fail: 1 invalid pass/fail invalid i/o3 not used 0 0 0 i /o4 not used 0 0 0 i/o5 not used 0 0 0 i/o6 page buffer ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o7 data cache ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o8 write protect not protected :1 protected: 0 write pro tect write protect write protect the pass/fail status on i/o1 and i/o2 is only valid during a program/erase operation when the device is in the ready state. chip status 1: during a auto page program or auto block erase operation this bit indicates the pa ss/fail result. during a auto page programming with data cache operation, this bit shows the pass/fail results of the current page program operation , and therefore this bit is only valid when i/o6 shows the ready state. chip status 2: this bit shows the p ass/fail result of the previous page program operation during auto page programming with data cache. this status is valid when i/o7 shows the ready state. the status output on the i/o6 is the same as that of i/o7 if the command input just before the 70h is not 15h or 31h . tabel 7 : f1h /f2h read status register definition definition page program block erase read i/o 1 pass : 0 , fail : 1 pass/fail pass/fail not use i/o 2 pass : 0 , fail : 1 plane0 pass/fail plane0 pass/fail not use i/o 3 pass : 0 , fail : 1 plane1 pass/fail plane1 pass/fail not use i/o 4 don t- cared not use not use not use i/o 5 don t- cared not use not use not use i/o 6 don t- cared not use not use not use i/o 7 busy : 0 , ready : 1 ready/busy ready/busy ready/busy i/o 8 protected : 0 , not protected : 1 write protect write protect write protect 201 1- 07 -01c 59
TH58NVG5S0FTA20 an application example with multiple devices is shown in the figure below. system design note: if the by/ry pin signals from multiple devices are wired together as shown in the diagram, the status read function can be used to determine the status of each individual device. reset the reset mode stops all operations. for example, in case of a program or erase operation, the internally generated voltage is discharged to 0 volt and the device enters the wait state. reset during a cache program/page copy may not just stop the most recent page program but it may also stop the previous program to a page depending on when the ff reset is input. the response to a ffh reset command input during the various device operations is as follows: when a reset (ffh) command is input during programming internal v pp 80 10 ff 00 by / ry t rst (max 30 s) device 1 cle 1 ce device 2 2 ce device 3 3 ce device n n ce device n + 1 1n ce + ale we re by / ry we re status on device 1 70h 1 ce ale i/o 70h status on device n by / ry cle n ce busy i/o1 to i/o8 201 1- 07 -01c 60
TH58NVG5S0FTA20 when a reset (ffh) command is input during erasing when a reset (ffh) command is input during read operation wh en a reset (ffh) command is input during ready when a status read command (70h) is input after a reset when two or more reset commands are input in succession 10 by / ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff i/o status : pass/fail pass : ready/busy ready ff 70 by / ry 00 ff 00 by / ry t rst (max 10 s) 30 internal erase voltage d0 ff 00 by / ry t rst (max 500 s) 00 by / ry t rst (max 10 s) ff 201 1- 07 -01c 61
TH58NVG5S0FTA20 application notes and comments (1) power - on/off sequence: the timing sequence shown in the figure below is necessary for the power - on/off sequence. the device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. during the initialization the device ready/busy signal indicates the busy state as shown in the figure below. in this time period, the acceptable commands are ffh or 70h / 71h/ f1h. the wp signal is useful for protecting against data corruption at power -on/off. (2) power - on reset the device goes i nto automatic self - initialization during power on if psl is tied either to gnd or nu. during the initialization process, the device consumes a maximum current of 30ma (i cco0 ). if psl is tied to v cc , the device will not complete its self - initialization duri ng power on and will not consume i cco0 , and completes the initialization process with the first reset command input after power on. during the first ffh reset busy period, the device consumes a maximum current of 30ma (i cco0 ). in either case (psl = gnd/nu or v cc ), the following sequence is necessary because some input signals may not be stable at power - on. (3) prohibition of unspecified commands the operation commands are listed in table 3. input of a command other than those specified in table 3 is prohibite d. stored data may be corrupted if an unknown command is entered during the command cycle. (4) restriction of commands while in the busy state during the busy state, do not input any command except 70h(71h , f1h ,f2h ) and ffh. ff reset power on v il operation 0 v v cc 2.7 v 2.5 v v il don t care don t care v ih ce , we , re wp cle, ale invalid don t care ready/busy 2 ms max 100 s max don t care invalid 2 ms max 100 s max 1ms 2 .7 v 2.5 v 0.5 v 0.5 v 201 1- 07 -01c 62
TH58NVG5S0FTA20 (5) acceptable commands after serial input command 80h once the serial input command 80h has been input, do not input any command other than the column address change in serial data input command 85h , auto program command 10h , multi page program command 11h , auto program with data c ache command 15h , or the reset command ffh. if a command other than 85h , 10h , 11h , 15h or ffh is input, the program operation is not performed and the device operation is set to the mode which the input command specifies. (6) a ddressing for program operation within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the block. random page address programming is prohibited. data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (1) (2) (3) (32) (64) data (64) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (2) (32) (3) (1) (64) data (64) ex.) random page program (prohibition) command other than 85h , 10 h , 11h , 15h or ffh 80 programming cannot be executed. 10 xx mode specified by the command. we by / ry 80 ff address input 201 1- 07 -01c 63
TH58NVG5S0FTA20 (7) status read during a read operation the device status can be read out by inputting the status read command 70h in read mode. once the device has been set to status read mode by a 70h command, the device will not return to read mode unless the read command 00h is input ted during [a]. if the read command 00h is input ted during [a], status read mode is reset, and the device returns to read mode. in this case, data output starts automatically from address n and address input is unnecessary (8) auto programming fa ilure (9) by/ry : termination for the ready/busy pin ( by/ry ) a pull - up resistor needs to be used for termination because the by/ry buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the pa ge to address n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 m n this data may vary from device to device. we recommend t hat you use this data as a reference when selecting a resistor value. v cc v cc device v ss r by / ry c l 1.5 s 1.0 s 0.5 s 0 1 k ? 4 k ? 3 k ? 2 k ? 15 ns 10 ns 5 ns t f t r r t r t f v cc = 3.3 v ta = 25 c c l = 10 0 p f t f ready v cc t r busy 00 address n command ce we by / ry re [a ] status read command input status read status output . 70 00 30 201 1- 07 -01c 64
TH58NVG5S0FTA20 (10) note regarding the wp signal the erase and program operations are automatically reset when wp goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din 201 1- 07 -01c 65
TH58NVG5S0FTA20 (11) when six address cycles are input although the device may read in a sixth address, it is ignored inside the chip. read operation program operation cle address input 00h ce we ale i/o by / ry ignored 30h cle ce we ale i/o address input ignored 80h data input 201 1- 07 -01c 66
TH58NVG5S0FTA20 (12) several programming cycles on the same page (partial page program) each segment can be programme d individually as follows: data pattern 4 data pattern 1 all 1 s all 1 s all 1 s all 1 s 1st programming 2nd programm ing 4th programming result data pattern 1 data pattern 2 data pattern 4 data pattern 2 201 1- 07 -01c 67
TH58NVG5S0FTA20 (13) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: please do not perform an erase operation to bad blocks. it may be impossible to recover the bad block information if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the performance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks over the device lifetime is as follows: min t y p. max unit valid (good) block number 16064 ? 1638 4 block bad block test flow regarding invalid blocks, b ad b lock m ark is in either the 1st or the 2nd page . * 1: no erase operation is allowed to detected bad blocks bad block bad block pass read check start bad block * 1 last block end yes fail block no = 1 no block no. = block no. + 1 read check : read either column 0 or 4096 of the 1st page or the 2nd page of each block. if the data o f the column is not ff (hex), define the block as a bad block. 201 1- 07 -01c 68
TH58NVG5S0FTA20 (14) failure phenomena for program and erase operations the devi ce may fail during a program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase block replacement page programming failure status read after program block replacement single bit programming failure 1 to 0 ecc ? ecc: error correction code. 4 bit correction per 528bytes is necessary. ? block replacement program erase when an error o ccurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using the device wh en the battery is low. power shortage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. (16) the number of valid blocks is on the basis of single plane operations, and this may be decreased with two pl ane operations. when an error happens in block a, try to reprogram the data into another block (block b) by loading from a n external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate scheme). block a block b error occurs buffer memory 201 1- 07 -01c 69
TH58NVG5S0FTA20 (17) reliability guidance this reliability guidance is intended to notify some guidance related to using nand flash with 4 bit ecc for each 512 bytes . for detailed reliability data, please refer to toshiba s reliability note. although random bit errors may occur during use, it does not necessarily mean that a block is bad. generally, a block should be marked as bad when a program status failure or erase status failure is detected. the other failure modes may be recovered by a block erase. ecc treatment for read data is mandatory due to the following data retention and read disturb failures. ? write/erase endurance write/erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either an auto pro gram or auto block erase operation. the cumulative b ad block count will increase along with the number of write/erase cycle s. ? data retention the data in memory may change after a certain amount of storage time. t his is due to charge loss or charge gain. after block erasure and reprogramming, the block may become usable again. here is the combined characteristics image of write/erase endurance and data retention. ? read disturb a read operation may disturb the data in memory . the da ta may change due to charge gain. usually , bit errors occur on other pages in the block, not the page being read. after a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to anothe r state. after block erasure and reprogramming, the block may become usable again. write/erase endurance [cycle s] data retention [ye ar s] 201 1- 07 -01c 70
TH58NVG5S0FTA20 package dimensions weight: 0.53g (typ.) 201 1- 07 -01c 71
TH58NVG5S0FTA20 revision history date rev. description 200 9 - 1 2 - 2 4 1.0 0 original version 20 10 - 06 - 10 1.0 0 ecc = tbd was changed to 4bit 20 10 - 08 - 02 1.0 0 chaned from tc58nvg3s 20 10 - 12 - 1 3 1.0 1 package was corrected from tsop i 48 - p - 1220 - 0.50 to tsop i 48 - p - 1220 - 0.50c 2011 - 07 - 01 1.10 deleted tentative notation. 201 1- 07 -01c 72
TH58NVG5S0FTA20 restrictions on product use ? toshiba corporation, and its subsidia ries and affiliates (collectively toshiba ), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively product ) without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba s written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including t he product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be used with or for. customers are solely responsible for all as pects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this docume nt. product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public i mpact ( uninten ded use ). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for unintended use unless specifically permitted in this document. ? do not disassemble, analyze, reverse - engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited unde r a ny applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no responsibility is assumed by toshiba for a ny infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provided in the relevant terms and conditions o f sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, consequential, special, or incidental damages or loss, including without limitation, loss of profits, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a parti cular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. export administration regulations. export and re - export of product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulation s. ? product is subject to foreign exchange and foreign trade control laws. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pr oduct. please use product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 201 1- 07 -01c 73

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